LUT Structure for Delay: Cluster or Cascade?
نویسنده
چکیده
This paper compares two types of lookup table (LUT) structures useful for delay optimization in programmable devices. Realistic assumptions about the input-to-output delays in a LUT and the delays of routable and nonroutable connections are used. The conclusion is that the cluster LUT structure results in better delays compared to the cascade structure. This LUT structure leads to mapped networks with a smaller ratio of near-critical outputs. Finally, it is easier to handle in the technology mapper.
منابع مشابه
Programmable Logic Device with an 8-stage cascade of 64K-bit Asynchronous SRAMs
The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs. 1. Introduction RAMs and PLAs (Programmable Logic Array) are used for p...
متن کاملUsing Sparse Crossbars within LUT Clusters
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, but has significant area overhead. This paper explores the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the LUT inputs. We have reduced the switch densities inside these m...
متن کاملLUT Cascades and Emulators for Realization of Logic Functions
Two types of programmable logic devices using LUTs (Look-Up Tables) are presented. An LUT cascade directly implements logic functions by a series connection of LUTs, while an emulator emulates an LUT cascade by sequentially accessing LUTs. The LUT cascade is faster, but has a limited logic capability, while the emulator is slower, but has a higher logic capability. LUT cascades and emulators ca...
متن کاملA Hybrid Logic Simulator Using LUT Cascade Emulators
This paper presents a hybrid logic simulator using both an event-driven and a cycle-based methods. For special primitives such as memories and tri-state buffers, it uses an event-driven method. For other parts, it uses a cyclebased method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones, and realizes each part by an LUT cascade emulator...
متن کاملA Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories
A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-mm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) mul...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2012